1. Field of the Invention
This invention relates to a system for improving the wire density in integrated circuit devices, such as chips and dies. In particular, this invention relates to the method and resulting structure for utilizing at least two lead frames to provide both peripheral and central area wiring to an integrated circuit device. Additionally, this invention employs an insulative adhesive tape to provide alignment, hold-down, and insulation for the lead frames.
2. Description of the Prior Art
Within the prior art a variety of devices are known for utilizing lead frame techniques in an attempt to improve wiring density and decrease production costs. For example U.S. Pat. No. 4,496,965 illustrates the use of two lead frames which are inter-digitated to improve the wiring density at the integrated circuit. That is, the leads from one frame alternate with the leads of from a second frame which are disposed in an essentially co-planar relationship. The lead frame patterns are stacked and joined into a co-planar configuration to increase the lead density at the semiconductor chip edge for peripheral bonding. The technique while improving bonding at the periphery of the device is not suitable for area wire bond capability or to provide engineering change capability at the periphery of the circuit board. Additionally, in the '965 patent, thermal performance is not enhanced because of the absence of lead frame lamination to the major surface of the semiconductor chip.
Reference is made to U.S. Pat. No. 3,999,285 which illustrates the use of a single lead frame separated by a pair of adhesive filled woven fiber mats. The technique while providing adhesive to bond the lead frame and therefore decrease manufacturing costs, does not employ plastic packaging techniques of the chip and, like the '965 patent does not provide for area wire bonding capability or engineering change capability of the periphery of the device circuit board. Other examples of the use of adhesive tape to maintain part alignment are illustrated in U.S. Pat. No. 4,480,150 wherein an adhesive is used to maintain part alignment orientation after tag trimming operations of the lead frame.
The use of adhesives in semiconductor devices for purposes of maintaining part alignment and therefore attempting to decrease manufacturing costs are illustrated in U.S. Pat. Nos. 3,871,018 and 4,461,924. In the '018 patent top metal and bottom metal base covers are cleaned/oxidized then coated with a high temperature glass frit layer. This is followed by additional low temperature glass frit application to the base lid which is reflow bonded to the lead frame. An epoxy coating on the top lid with the lead frame attachment creates a metal package enclosure. In the '924 patent the package employs a top metal housing in a bottom metal base. The single lead frame is adhesively bonded to both sides of the top and bottom base and cover metals to create a metal package enclosure.
Other examples of tab bonding utilizing tape or a single level lead frame utilizing an alternative technique to maintain alignment, springs are illustrated respectively in U.S. Pat. Nos. 4,438,181 and 3,621,114.
While the prior art is replete with a number of concepts to utilize single lead frames held by an adhesive or, having essentially co-planar multiple lead frame technologies, the prior art is devoid of any recognition that vertically displaced lead frames can be used to provide not only peripheral but center bonding to semiconductor devices. Additionally, while the prior art recognizes the use of plastic molding of the completed lead frame and integrated circuit device, such as used in the context of a co-planar lead frame technology.
A solution to many of these problems is achieved in the system described and claimed in commonly assigned U.S. patent application Ser. No. 940,235 filed Dec. 8, 1986 and entitled "Package Semiconductor Chip." In the system proposed in that application a lead frame is adhesively attached to a major surface of a semiconductor chip, such as the top surface. A dielectric layer serving as an alpha barrier is placed between the chip and the lead frame and joined to both. Wires are used to establish contact to terminal pads on the center of the semiconductor chip. This system represents a material advance by providing access to the center portion of the chip. However, increased lead density and access to both the center and periphery of the chip remain as problems.